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| 18, 4V PRELIMINARY CY7B9514V 3.3V Quad SONET Transceiver Features * SONET/SDH and ATM Compatible * Clock and data recovery from 51.84- or 155.52-MHz datastream * 155.52-MHz clock multiplication from 19.44-MHz source * 51.84-MHz clock multiplication from 6.48-MHz source * 1% frequency agility * Line Receiver Inputs: No external buffering required * Differential output buffering * 100K PECL compatible I/O * No output clock "drift" without data transitions * Link Status Indication * Loop-back testing * Dual reference clock inputs and reference clock output * Transition between REFCLKs is slowed to prevent data recovery errors * Single +3.3V 10% supply * 100-pin TQFP * Compatible with fiber-optic modules, coaxial cable, and twisted pair media * Power-down options to minimize power or crosstalk * Low operating current: <400 mA * 0.8 BiCMOS Functional Description The Quad PMD ATM Transceiver is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ or NRZI serial data stream and to provide differential data buffering for the Transmit side of the system. Pin Configuration AVCC_RX2 EAVCC_TX2 TOUT2TOUT2+ AVCC_P3 AVSS_P3 RIN1+ RIN1- AVSS_RX1 FC1+ FC1- CD1 AVCC_RX1 EAVCC_TX1 TOUT1- TOUT1+ AVSS_RX0 RIN0+ RIN0- AVCC_RX0 CD2 FC2- FC2+ AVSS_RX2 RIN2- RIN2+ EAVCC_TX3 TOUT3+ TOUT3- AVCC_RX3 CD3 FC3- FC3+ AVSS_RX3 RIN3- RIN3+ DVCC REFOUT LFI3 LFI2 LFI1 LFI0 DVSS RCLK3- RCLK3+ EAVCC_RX3 RSER3- RSER3+ AVCC_P2 AVSS_P2 1 3 77 5 75 7 73 9 71 11 69 13 15 17 63 19 61 21 59 23 57 25 55 27 53 29 33 35 37 39 41 43 45 47 49 51 99 97 95 93 91 89 87 85 83 81 79 CY7B9514V 67 65 FC0+ FC0- CD0 AVSS_P4 TOUT0- TOUT0+ EAVCC_TX0 AVCC_P4 TCLK+ TCLK- EAVCC_TCLK TSER3- TSER3+ PWR_DWN TSER2- TSER2+ AVCC_TX TSER1- TSER1+ AVSS_TX FC_TX+ FC_TX- MODE1 TSER0- TSER0+ REFSEL REFCLK0 REFCLK1 LOOP0 LOOP1 7B9514V-1 Cypress Semiconductor Corporation RSER2- RSER2+ EAVCC_RX2 RCLK2- RCLK2+ MODE0 RCLK1- RCLK1+ EAVCC_RX1 RSER1- RSER1+ AVSS_P1 AVCC_P1 RSER0- RSER0+ EAVCC_RX0 RCLK0- RCLK0+ LOOP3 LOOP2 * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 September 8, 1998 PRELIMINARY Logic Block Diagram CY7B9514V LOOP0 RIN0+ RIN0- RCLK0+ RCLK0- RSER0+ RSER0- LFI0 TSER0+ TSER0- PLL CD0 TOUT0+ TOUT0- Channel 0 LOOP1 RIN1+ RIN1- PLL RCLK1+ RCLK1- RSER1+ RSER1- LFI1 TSER1+ TSER1- CD1 TOUT1+ TOUT1- Channel 1 LOOP2 RIN2+ RIN2- PLL RCLK2+ RCLK2- RSER2+ RSER2- LFI2 TSER2+ TSER2- CD2 TOUT2+ TOUT2- Channel 2 LOOP3 RIN3+ RIN3- PLL RCLK3+ RCLK3- RSER3+ RSER3- LFI3 TSER3+ TSER3- CD3 TOUT3+ TOUT3- Channel 3 REFSEL REFCLK0 REFCLK1 Control & Test PLL x8 REFOUT TCLK+ TCLK- PWR_DWN MODE1 MODE0 7B9514V-2 2 PRELIMINARY CY7B9514V Link Fault Indication Fiber or Copper ReceiveSerial Data Media Interface Carrier Detect Recovered Clock Recovered Serial Data TransmitSerial Data Bit Rate Clock Link Fault Indication Recovered Clock Recovered Serial Data TransmitSerial Data Serial to Parallel Conversion and Framing Parallel to Serial Conversion Serial to Parallel Conversion and Framing Parallel to Serial Conversion Serial to Parallel Conversion and Framing Parallel to Serial Conversion Serial to Parallel Conversion and Framing Parallel to Serial Conversion Receive ParallelData ReceiveStart of Cell Read Strobe SONET/ SDH Overhead Processing ATM Cell Processing Address TransmitParallel Data Transmit tart of Cell S Read Strobe Fiber or Copper Media Interface Buffered Transmit Data Fiber or Copper ReceiveSerial Data Media Interface Carrier Detect Fiber or Copper Media Interface Buffered Transmit Data SONET/ SDH Overhead Processing ATM Cell Processing CY7B9514V Fiber or Copper ReceiveSerial Data Media Interface Carrier Detect SONET/ SDH Serial Transceiver Bit Rate Clock Link Fault Indication RecoveredClock RecoveredSerial Data Packet Reassembly or ATMSwitch Core SONET/ SDH Overhead Processing ATM Cell Processing Fiber or Copper Media Interface Buffered Transmit Data TransmitSerial Data Bit Rate Clock Link Fault Indication Recovered Clock Recovered Serial Data Fiber or Copper ReceiveSerial Data Media Interface Carrier Detect Fiber or Copper Media Interface Buffered Transmit Data TransmitSerial Data Bit Rate Clock Ref Clk Output to MUX Logic SONET/ SDH Overhead Processing ATM Cell Processing Byte Rate Oscillator Clk Select From Local Control Byte Rate Clock From Back Plane Quad UNI Processor Igt WAC-413 VNS 67200 or 4 UNI Processor PMC-Sierra PM5345 IgT WAC-013 Rockwell BT8222 UTOPIA Level 2 Bus Connections When using 4 single UNI Processors 7B9514V-3 Figure 1. SONET/SDH and ATM Interface 3 PRELIMINARY Pin Descriptions Name RIN0 RIN1 RIN2 RIN3 RSER0 RSER1 RSER2 RSER3 RCLK0 RCLK1 RCLK2 RCLK3 CD0 CD1 CD2 CD3 I/O Description CY7B9514V Differential In Receive Input. This line receiver port connects the receive differential serial input data stream to the internal Receive PLL. This PLL will recover the embedded clock (RCLK) and data (RSER) information for one of two data rates depending on the state of the MODE pin. These inputs can receive very low amplitude signals and are compatible with all PECL signaling levels. If the RIN inputs are not being used, connect RIN+ to VCC and RIN- to VSS. PECL Out Differential Recovered Serial Data. These PECL 100K outputs (+3.3V referenced) are the recovered data from the input data stream (RIN). This recovered data is aligned with the recovered clock (RCLK) with a set-up and hold window compatible with most data processing devices. All PECL outputs can be powered down by connecting both outputs to VCC or by leaving them both unconnected. Recovered Clock. These PECL 100K outputs (+3.3V referenced) are the recovered clock from the input data stream (RIN). This recovered clock is used to sample the recovered data (RSER) and is timing compatible with most data processing devices. If both the RSER and the RCLK are tied to VCC or left unconnected, the entire Receive PLL will be powered down. PECL Out Differential PECL In Carrier Detect. These inputs control the recovery function of the Receive PLLs and can be driven Single Ended by the carrier detect outputs from optical modules or from external transition detection circuitry. When this input is at a PECL HIGH, the input data stream (RIN) is recovered normally by the Receive PLL. When this input is at a PECL LOW, the Receive PLL no longer aligns to RIN, but instead aligns with the REFCLKx8 frequency. Also, the Link Fault Indicator (LFI) will transition LOW, and the recovered data outputs (RSER) will remain LOW regardless of the signal level on the Receive data-stream inputs (RIN). Each CD input has an internal pull-down resistor. LVTTL Out Link Fault Indicator. These outputs indicate the status of the input data stream (RIN). It is controlled by three functions; the Carrier Detect (CD) input, the internal Transition Detector, and the Out of Lock (OOL) detector. The Transition Detector determines if RIN contains enough transitions to be accurately recovered by the Receive PLL. The Out-of-Lock detector determines if RIN is within the frequency range of the Receive PLL. When CD is HIGH and RIN has sufficient transitions and is within the frequency range of the Receive PLL, the LFI output will be HIGH. If CD is at a PECL LOW or RIN does not contain sufficient transitions or RIN is outside the frequency range of the Receive PLL then the LFI output will be LOW (see MODE1). LFI0 LFI1 LFI2 LFI3 TSER0 TSER1 TSER2 TSER3 TOUT0 TOUT1 TOUT2 TOUT3 REFCLK0 REFCLK1 Differential In Transmit Serial Data. This line receiver port connects the transmit differential serial input data stream to the TOUT transmit buffers. Depending on the state of the LOOP pin, this input port can also be set up to supply the serial input data stream to the Receive PLL. These inputs can receive very low amplitude signals and are compatible with all PECL signaling levels. If the TSER inputs are not being used, connect TSER+ to VCC and TSER- to VSS. PECL Out Differential Transmit Output. These PECL 100K outputs (+3.3V referenced) are the buffered version of the Transmit data stream (TSER). This Transmit path is used to take weak input signals and rebuffer them to drive low-impedance copper media or fiber-optic modules. All PECL outputs can be powered down by connecting both outputs to VCC or by leaving them both unconnected. Reference Clocks. One of these inputs is selected by the REFSEL pin as the clock frequency reference for the clock and data recovery Receive PLL. REFCLK is multiplied internally by eight and sets the approximate center frequency for the internal Receive PLL to track the incoming bit stream. This input is also multiplied by eight by the frequency multiplier Transmit PLL to produce the bit rate Transmit Clock (TCLK). REFCLK can be connected to a TTL frequency source. Transmit Clock. These PECL 100K outputs (+3.3V referenced) provide the bit rate frequency source for external Transmit data processing devices. This output is synthesized by the Transmit PLL and is derived by multiplying the REFCLK frequency by eight. When this output is turned off, the entire Transmit PLL is powered down. All PECL outputs can be powered down by connecting both outputs to VCC or by leaving them both unconnected. Loop Back Select. This input is used to select the input data stream source that the Receive PLL uses for clock and data recovery. When the LOOP input is HIGH, the Receive input data stream (RIN) is used for clock and data recovery. When LOOP is LOW, the Transmit input data stream (TSER) is used by the Receive PLL for clock and data recovery. LVTTL In TCLK PECL Out Differential LOOP0 LOOP1 LOOP2 LOOP3 LVTTL In 4 PRELIMINARY Pin Descriptions (continued) Name MODE0 I/O 3-Level In Description CY7B9514V Frequency Mode Select. This three-level input selects the frequency range for the clock and data recovery Receive PLL and the frequency multiplier Transmit PLL. When this input is held HIGH (VCC) the PLLs operate at the SONET (SDH) STS-3 (STM-1) line rate of 155.52 MHz. When this input is held LOW (VSS) the PLLs operate at the SONET STS-1 line rate of 51.84 MHz. The REFCLK frequency in both operating modes is 1/8 the PLL operating frequency. When the MODE0 input is left floating or held at VCC/2, the TSER inputs substitute for the internal PLL VCO for use in factory testing. MODE1 enables the transition detector when it is held HIGH (VCC). The transition detector is disabled when MODE1 is held LOW (VSS). When the MODE1 input is left floating or held at VCC/2, the factory test mode is enabled. MODE1 3-Level In FC0 FC1 FC2 FC3 FC_TXP FC_TXN REFOUT External 1-F These external capacitors are used only to reduce the PLL bandwidth and peaking, when desired. caps The PLL lock time will also be increased. External 1-F These external capacitors are used only when the slew rate between the two REFCLKs needs to caps be reduced. LVTTL Out Reference Output. This output is a buffered version of the selected reference clock. Depending on the state of the REFSEL pin this output can be a buffered version of REFCLK1 and REFCLK2. When there is a change of state at the REFSEL, this output will change over from one reference clock to another reference clock smoothly without glitch, except if TCLK outputs are held HIGH or left floating. Reference Select. This pin selects one of the external reference clock (REFCLK 0/1) to be used as the internal reference clock for the Transmit and Receive PLLs. When this input is at a TTL HIGH, REFCLK1 is selected. When this input is at a TTL LOW, REFCLK0 is selected. Power Down. This pin will power down all the PLLs and logic components of the device. When this pin is held LOW, the Transmit PLL, transition detection logic, and Receive PLLs will power down. When this pin is held HIGH, the Transmit PLL, transition detection logic, and Receive PLLs will resume normal operation. Analog Power. Power pins for the PECL drivers for the TOUT outputs. These pins must be connected to a well decoupled 3.3V DC supply. REFSEL LVTTL In PWR_DWN LVTTL In EAVCC_TX0 EAVCC_TX1 EAVCC_TX2 EAVCC_TX3 AVCC_P1 AVCC_P2 AVCC_P3 AVCC_P4 AVCC_RX0 AVCC_RX1 AVCC_RX2 AVCC_RX3 AVCC_TX AVSS_P1 AVSS_P2 AVSS_P3 AVSS_P4 AVSS_RX0 AVSS_RX1 AVSS_RX2 AVSS_RX3 AVSS_TX EAVCC_RX0 EAVCC_RX1 EAVCC_RX2 EAVCC_RX3 Power Power Analog Power. Power pins for the analog portion of the Receive and Transmit PLLs. Gnd Analog Ground. Ground pins for the analog portion of the Receive and Transmit PLLs. Power Analog Power. Power for the PECL RSER and RCLK outputs.These pins must be connected to a well decoupled +3.3V DC supply. 5 PRELIMINARY Pin Descriptions (continued) Name I/O Description EAVCC_TCLK Power DVCC DVSS Power Gnd CY7B9514V Analog Power. Power pin for the TCLK PECL drivers. This pin must be connected to a well decoupled +3.3V DC supply. Digital Power. Power pin for the digital logic of the device. This pin must be connected to a well decoupled 3.3V DC supply. Digital Ground. Ground pin for the digital logic of the device. Receive Functions The CY7B9514V has four receiver channels. The primary function of the receivers is to recover clock (RCLK) and data (RSER) from the four different incoming differential PECL data streams (RIN) without the need for external buffering. These built-in line receiver inputs, as well as the TSER inputs mentioned above, have a wide common-mode range (1.25V) and the ability to receive signals with as little as 50 mV differential voltage. They are compatible with all PECL signals and any copper media. The clock recovery function is performed using embedded PLLs. The recovered clock is not only passed to the RCLK outputs, but also used internally to sample the input serial data stream in order to recover the data pattern. The Receive PLL uses the selected REFCLK input as a byte-rate reference. This input is multiplied by 8 (REFCLKx8) and is used to improve PLL lock time and to provide a center frequency for operation in the absence of input data stream transitions. The receiver can recover clock and data in two different frequency ranges depending on the state of the three-level MODE0 pin as explained earlier. To insure accurate data and clock recovery, REFCLKx8 must be within 250 ppm of the transmit bit rate. The standards, however, specify that the REFCLKx8 frequency accuracy be within 20-100 ppm. Carrier Detect (CD) and Link Fault Indicator (LFI) Functions The Link Fault Indicator (LFI) outputs are LVTTL-level outputs that indicate the status of each of the four receivers. These outputs can be used by an external controller for Loss of Signal (LOS), Loss of Frame (LOF), or Out of Frame (OOF) indications. Each LFI output is controlled by the respective Carrier Detect (CD) input, the internal Transitions Detector, and the PLL Out of Lock (OOL) circuitry. Each CD input may be driven by external circuitry that is monitoring the respective incoming data stream. Optical modules have CD outputs that indicate the presence of light on the optical fiber and some copper based systems use external threshold detection circuitry to monitor the incoming data stream. The CD input is a 100K PECL compatible signal that should be held HIGH when the incoming data stream is valid. When CD is pulled to a 3.3V PECL LOW (<1.475V Max.), the LFI output will transition LOW and the Receiver PLL will align itself with the REFCLKx8 frequency and the recovered data outputs (RSER) will remain LOW regardless of the signal level on the Receive data-stream inputs (RIN). In addition, the CY7B9514V has four built-in transition detectors for each channel that also check the quality of the incoming data stream. The absence of data transitions can be caused by a broken transmission media, a broken transmitter, or a problem with the transmit or receive media coupling. The CY7B9514V will detect a quiet link by counting the number of Description The CY7B9514V Quad Local Area Network ATM Transceiver can be used in both SONET/SDH and ATM applications to recover clock and data information from four 155.52-MHz or 51.84-MHz NRZ (Non Return to Zero) or NRZI (Non Return to Zero Invert on ones) serial data streams. A byte-rate reference clock is provided by buffering one of the two reference clock sources.This device also provides a bit-rate Transmit clock, by multiplying the buffered byte-rate reference clock through the use of a frequency multiplier PLL and four channels of differential data buffering for the Transmit side of the system (see Figure 1). Operating Frequency The CY7B9514V operates at either of two frequency ranges. The MODE0 input selects which of the two frequency ranges the Transmit frequency multiplier PLL and the Receive clock and data recovery PLLs in all four channels will operate at. The MODE0 input has three different functional selections. When MODE0 is connected to V CC, the highest operating range of the device is selected. The device has two reference clock inputs, REFCLK0 and REFCLK1. REFSEL is used to select which clock input is used to serve as a reference source for the Transmit frequency multiplier PLL and the Receive clock and data recovery PLLs. A 19.44-MHz 1% source must drive the selected REFCLK input and the five PLLs will multiply this rate by 8 to provide output clocks that operate at 155.52 MHz 1%. When the MODE0 input is connected to ground (GND), the lowest operating range of the device is selected. A 6.48-MHz 1% source must drive the selected REFCLK input and the five PLLs will multiply this rate by 8 to provide output clocks that operate at 51.84 MHz 1%. When the MODE0 input is left unconnected or forced to approximately VCC/2, the device enters a factory test mode. Transmit Functions The transmit section of the CY7B9514V contains a PLL that takes the selected REFCLK input and multiplies it by 8 (REFCLKx8) to produce a PECL (Pseudo ECL) differential output clock (TCLK). The transmitter has two operating ranges that are selectable with the three-level MODE0 pin as explained above. The CY7B9514V Transmit frequency multiplier PLL allows low-cost byte rate clock sources to be used to time the upstream serial data transmitter as shown in Figure 1. Both of the REFCLK inputs are LVTTL-level inputs, allowing them to be driven by low-cost TTL crystal oscillators, or any TTL-level clock source. The four Transmit PECL differential input pairs (TSER) are buffered by the CY7B9514V yielding the differential data outputs (TOUT). These outputs can be used to directly drive transmission media such as Printed Circuit Board (PCB) traces, optical drivers, twisted pair, or coaxial cable. 6 PRELIMINARY bit times that have passed without a data transition. A bit time is defined as the period of RCLK. When 512 bit times have passed without a data transition on RIN, LFI will transition LOW. The receiver will assume that the serial data stream is invalid, and, instead of allowing the RCLK frequency to wander in the absence of data, the PLL will lock to the REFCLK*8 frequency. This will insure that RCLK is as close to the correct link operating frequency as the REFCLK accuracy. LFI will be driven HIGH, and the receiver will recover clock and data from the incoming data stream when the transition detection circuitry determines that at least 64 transitions have been detected within 256 bit-times. The transition detector is disabled when MODE1 is held LOW (VSS). Loop Back Testing The LVTTL level LOOP pins are used to perform loop-back testing. When LOOP is asserted (held LOW) the Transmit serial input (TSER) is used by the respective Receiver PLL for clock and data recovery. This allows in-system testing to be performed on each clock and data recovery PLL and transition detection logic. When a channel is in loop-back mode the state of the CD pin is ignored. For example, an ATM controller can present ATM cells to the input of the ATM cell processor and check to see that these same cells are received from each of the four channels. When the LOOP input is deasserted (held HIGH) the Receive PLL is once again connected to the Receiver serial inputs (RIN). The LOOP feature can also be used in applications where clock and data recovery are to be performed from either of two data streams from each channel. In these systems the LOOP pin is used to select whether the TSER or the RIN inputs are used by the Receive PLL for clock and data recovery. Power-Down Modes There are several power-down features on the CY7B9514V. Any of the differential output drivers can be powered down by either tying both outputs to VCC or by simply leaving them unconnected where internal pull-up resistors will force these outputs to VCC. This will save approximately 4 mA per output pair in addition to the associated output load current. If the TOUT outputs are tied to VCC or left unconnected, the Transmit buffer path will be turned off. If the TCLK outputs are tied to VCC or left unconnected, the entire Transmit PLL will be powered down. For each receive channel, by leaving both the RCLK and RSER outputs unconnected or tied to VCC, the corresponding Receive PLL is turned off. Besides the option of turning off drivers and PLLs selectively, the PWR_DWN pin can also be used to power down the entire device. When PWR_DWN pin is at TTL LOW, the Transmit PLL, transition detection logic and all four Receive PLLs will be powered down (see application section concerning PECL output loading when PWR_DWN is asserted). When the PWR_DWN pin is at TTL HIGH, the Transmit PLL, transition detection logic, and all four Receive PLLs will be enabled. CY7B9514V vice can also be used in data mover and Local Area Network (LAN) applications that operate at these frequencies. The CY7B9514V can provide clock and data recovery as well as output buffering for physical layer protocol engines such as the SONET/SDH and ATM processing application shown in Figure 1. Figure 1 shows the CY7B9514V in an ATM system that uses the IgT WAC-413 device. The CY7B9514V will recover clock and data from the input serial data streams and pass them to the WAC-413. The WAC-413 device will perform serial to parallel conversion on each channel, SONET/SDH overhead processing, and ATM cell processing and then pass ATM cells to an ATM packet reassembly engine. On the Transmit side, a segmentation engine will divide long packets of data such as Ethernet packets into 53 byte cells and pass them to each of the channels of the WAC-413. The WAC-413 device will then perform ATM cell processing, such as header generation, SONET/SDH overhead processing, and parallel to serial conversion on each channel. These serial data streams will then be passed to the CY7B9514V, which will buffer these data streams and pass them along to the transmission media. The CY7B9514V provides the necessary clock and data recovery function to the WAC-413. These differential PECL clock and data signals interface directly with the RS_SER_DATA and RS_SER_CLK inputs of the WAC-413 device as shown in Figure 1. In addition, the CY7B9514V provides transmit data output buffering for direct drive of cable transmission media. The CY7B9514V has two local reference clock inputs. An internal mux controls which input clock is used as the reference. Changing from one input to the other will happen smoothly without glitch on REFOUT. Therefore, a low-cost crystal oscillator can drive one input, and a clock from another external clock source, e.g., a distributed clock from a central clock board, can drive the other clock input. Another application of the two clock inputs is feeding a 19.44-MHz clock to one input and a 6.48-MHz to the other clock input, so now the CY7B9514V can operate at both STS-1/OC-1 rate as well as STS-3/OC-3/STM-1 rate by configuring the MODE0 pin and REFSEL pin to the appropriate state. Lastly, the CY7B9514V provides a bit rate reference clock to the WAC-413 transmitter by multiplying one of the two local reference clocks by eight. Utilized PECL outputs must be terminated by external resistors at the end of the connected transmission line. Figure 2 shows an example of terminating a 50 transmission line connected to a pair of PECL outputs. CY7B9514V offers a Power-Down feature. When the PWR_DWN input is asserted (to a TTL LOW), the Transmit PLL, transition detection logic, and Receive PLLs will power down. When this power-down feature is used, a power-down control circuit shall be implemented at each PECL output termination as shown in Figure 3. Each power-down control block will connect the terminating resistors to ground in normal operating mode. The pass gate, shown in Figure 3, must be able to sink at least 25 mA when turned on. It also provides a low resistance path to ground. In power-down mode, the power-down control circuit will allow the terminating resistors to pull both outputs to VCC. The power-down control logic should consume minimal power when in power-down mode (i.e., PWR_DWN asserted). A CMOS device is suitable to implement the power down control logic. CYBUS3384 is a good candidate for this application. Applications The CY7B9514V can be used in Local Area Network ATM applications. The operating frequency of the CY7B9514V is centered around the SONET/SDH STS-1 rate of 51.84 MHz and the SONET/SDH STS-3/STM-1 rate of 155.52 MHz. This de- 7 PRELIMINARY Termination Network CY7B9514V Zo=50 OUTPUT+ OUTPUT- Zo=50 50 50 50 VCC 470 pF CY7B9514V Figure 2. Termination Network Design Termination Network CY7B9514V Zo=50 OUTPUT+ OUTPUT- Zo=50 50 50 50 VCC 470 pF Power Down Control (CYBUS3384) PWR_DWN PWR_DWN Figure 3. Power Down Control System Block (one terminated output) Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied .................................................. -55C to +125C Supply Voltage to Ground Potential..................-0.5V to +5.0V DC Input Voltage ................................. -0.5V to + (V CC + 0.5)V Output Current into TTL Outputs (LOW)...................... 30 mA Output Current into ECL Outputs (HIGH).....................-50 mA Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Latch-Up Current .....................................................>200 mA Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 10% 3.3V 10% 8 PRELIMINARY Electrical Characteristics Over the Operating Range Parameter VIHT VILT IIHT IILT VOHT VOLT IIHE IILE [1] CY7B9514V Description Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage PECL Input HIGH Current PECL Input LOW Current Input High Voltage Input LOW Voltage Input Differential Voltage PECL Output HIGH Voltage PECL Output LOW Voltage Output Differential Voltage Three-Level Input HIGH Three-Level Input MID [2] Test Condition Min. 2.0 -0.5 Max. VCC 0.8 +50 +50 Unit V V A A V TTL Compatible Input Pins (LOOP, REFCLK, REFSEL, PWR_DWN) VIN=VCC VIN=0.0V IOH=-2 mA IOL=4 mA CD TSER/RIN CD TSER/RIN CD TSER/RIN CD TSER/RIN TSER/RIN Test Load=50 to VCC - 2V T > 0C VIN=VIHE(MAX) VIN=VIHE(MAX) VIN=1.3V VIN=VILE(MIN) -50 -50 2.4 TTL Compatible Output Pins (LFI, REFOUT) 0.45 +0.5 -250 +0.5 -250 VCC - 1.145 0 1.3 100 1200 VCC - 0.83 VCC - 1.96 0.6 VCC - 0.6 VCC/2 - 0.3 0.0 VCC VCC/2 + 0.3 0.6 400 PWR_DWN = LOW PECLOUT pins are forced to VOH 20 +300 +250 +300 +250 VCC VCC VCC - 1.475 V A A A A V V V V mV V V V V V V mA mA PECL Compatible Input Pins (CD, TSER, RIN) VIHE VILE VIDIFF VOHE VOLE VODIFF VIHH VIMM VILL ICCM ISTBY PECL Compatible Output Pins (RCLK, RSER, TOUT, TCLK) Three-Level Input Pins (MODE0 MODE1) Three-Level Input LOW Total Operating Current. Excluding output currents[3] Standby Current Operating Current[3] Capacitance[4] Parameter CIN Description Input Capacitance Test Conditions TA = 25C, f0 = 1 MHz, VCC = 3.3V Max. 10 Unit pF Notes: 1. Input currents are always positive at all voltages above VCC/2. 2. No more than 5 A leakage when held at MID level. 3. For each active received channel not active (i.e., RSERx & RCLKx tied to VCC or left floating) the ICCM is reduced by 65 mA. For each transmit channel with the outputs tied to VCC or left floating, ICCM is reduced by 7 mA. If TCLK outputs are tied to VCC or left floating, reduce ICCM by 37mA. 4. Tested initially and after any design or process changes that may affect these parameters. 9 PRELIMINARY AC Test Loads and Waveforms 3.3V OUTPUT R1 = 620 R2 = 680 CL < 30 pF (Includes fixture and probe capacitance) R1 CL R2 CL RL VCC - 2 CY7B9514V RL = 50 CL < 5 pF (Includes fixture and probe capacitance) 7B9514V-7 (a) TTL AC Test Load 3.0V 3.0V 2.0V GND < 1 ns 1.0V 2.0V [5] (b) PECL AC Test Load [5] VIHE 80% VILE 20% 1.0V < 1 ns 7B9514V-5 VIHE 80% 20% VILE < 1 ns 7B9514V-6 < 1 ns (c) TTL Input Test Waveform (d) PECL Input Test Waveform Note: 5. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only. h 10 PRELIMINARY Switching Characteristics Over the Operating Range Parameter fREF tB tPE tODC tRF tLOCK tRPWH tRPWL tDV tDH tPD tRL Reference Frequency Bit Time[6] Receiver Static Phase Error [4] CY7B9514V Description MODE0=LOW MODE0=HIGH MODE0=LOW MODE0=HIGH MODE0=LOW MODE0=HIGH Output Duty Cycle (TCLK, RCLK)[4] Output Rise/Fall Time [4] [7] Min. 6.41 19.24 19.50 6.50 Max. 6.55 19.64 19.10 6.40 200 200 Unit MHz MHz ns ns ps ps % ns s s ns ns ns ns 45 0.4 MODE0=LOW MODE0=HIGH 10 10 3 1 55 1.2 3000 1000 PLL Lock Time (RIN transition density 25%) REFCLK Pulse Width HIGH REFCLK Pulse Width LOW Data Valid Data Hold Propagation Delay (TSER to TOUT)[8] No Transition Run Length, 25% data field 10 75 ns fB Notes: 6. tB is calculated as 1/(fREF X8). 7. tLOCK is the time needed for transitioning from lock to REFCLK X8 to lock to data. 8. The PECL switching threshold is the differential zero crossing (i.e., the place where + and - signals cross). Switching Waveforms tRPWL tRPWH REFCLK 7B9514V-8 TSER tPD TOUT 7B9514V-9 11 PRELIMINARY Switching Waveforms (continued) tODC tODC CY7B9514V RCLK+ tDV RSER tDH 7B9514V-10 tB/2RIN tPE tB/2- tPE 7B9514V-11 Ordering Information Ordering Code CY7B9514V-AC Document #: 38-00648-D Package Name A101 Package Type 100-Lead (14 X 20 mm) Molded TQFP OperatingRange Commercial 12 PRELIMINARY * CY7B9514V Package Diagram T 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A (c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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